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Integrated Circuit Systems, Inc.
ICS839893I
LOW SKEW, 1-TO-13 LVCMOS/LVTTL BUFFER DIVIDER
FEATURES
* 13 LVCMOS/LVTTL outputs: 3 banks (6, 6, 1 outputs per bank respectively) * Selectable CLK0 or CLK1 LVCMOS/LVTTL clock inputs * CLK0, CLK1 supports the following input types: LVCMOS, LVTTL * Maximum output frequency: 250MHz * Output skew: 40ps (maximum), within bank * Full 3.3V or 2.5V operating supply * -40C to 85C ambient operating temperature * Available in both, Standard and RoHS/Lead-Free compliant packages
GENERAL DESCRIPTION
The ICS839893I is a high-performance one to thirteen LVCMOS/LVTTL buffer/divider and is HiPerClockSTM a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The device has two selectable LVCMOS/LVTTL clock inputs and it generates 13 new LVCMOS/LVTTL clock outputs. The first bank of six outputs offers divide-by-1, 2, 4, 8 or 16. The second bank of six outputs can be configured to the same divide ratio as the first bank, or with an additional divide-by-two. The first two banks can be placed into a highimpedance output state with the assertion of a LOW on the nOE/MR input. One additional output can be configured to divide-by-4, 6, 8 or 16. This device is functional with full 3.3V or full 2.5V supplies.
IC S
SIMPLIFIED BLOCK DIAGRAM
nOE/MR
PIN ASSIGNMENT
VDD nc REF_SEL nc GND FSEL0 FSEL1 GND FSEL2 FSEL3 nOE/MR VDD
FSEL0 FSEL1 FSEL2 QA FSEL0 FSEL1 FSEL2 QA 0 0 0 /1
0
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
/1 /2 /2 /4 /2 /16 /8 /4
CLK0 CLK1 REF_SEL
0 1
0 0 0 1 1 1 1
DQ
0
/2
FSEL0 FSEL1 FSEL2 QC 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 /8 /8 /6 /8 /4 /16 /8 /4
1
DQ
DQ
GND QA0:QA5 QA0 QA1 VDDO_A GND QA2 QB0:QB5 QA3 VDDO_A GND QA4 QA5 VDDO_A QC
36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 41 20 48-Pin LQFP 42 7mm x 7mm x 1.4mm 19 43 18 body package 17 44 Y Package 45 16 46 15 Top View 14 47 48 13 1 2 3 4 5 6 7 8 9 10 11 12
ICS839893I
GND QB0 QB1 VDDO_B GND QB2 QB3 VDDO_B GND QB4 QB5 VDDO_B
FSEL[0:2]
FSEL3
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GND QC nc nc VDDO_C CLK0 CLK1 VDD nc nc nc GND
REV. A AUGUST 8, 2005
Integrated Circuit Systems, Inc.
ICS839893I
LOW SKEW, 1-TO-13 LVCMOS/LVTTL BUFFER DIVIDER
Type Power Output Unused Power Input Power Power Output Description Supply ground. Bank C output. LVCMOS / LVTTL interface levels. No connect. Output supply pin for Bank C output. Pulldown LVCMOS / LVTTL clock inputs. Core supply pins. Output supply pins for Bank B outputs. Bank B outputs. LVCMOS / LVTTL interface levels. Active High Master Reset. Active Low Output Enable. When logic LOW, the internal dividers and the outputs are Pulldown enabled. When logic HIGH, the internal dividers are reset and the outputs are tri-stated (HiZ). LVCMOS / LVTTL interface levels. Pulldown Clock frequency selection and configuration of clock divider modes. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 12, 16, 20, 24, 29, 32, 37, 41, 45 2 3, 4, 9, 10, 11, 33, 35 5 6, 7 8, 25, 36 13, 17, 21 14, 15, 18, 19, 22, 23 Name GND QC nc VDDO_C CLK0, CLK1 VDD VDDO_B QB5, QB4 QB3, QB2 QB1, QB0
26
nOE/MR
Input
27, 28, 30, 31 34 38, 39 42, 43, 46, 47 40, 44, 48
FSEL3, FSEL2, FSEL1, FSEL0 REF_SEL QA0, QA1, QA2, QA3, QA4, QA5 VDDO_A
Input
Input
Selects the primar y reference clock. When LOW, selects CLK0 Pulldown as the primar y clock source. When HIGH, selects CLK1 as the primar y clock source. LVCMOS / LVTTL interface levels. Bank A outputs. LVCMOS / LVTTL interface levels. Output supply pins for Bank A outputs.
Output Power
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pulldown Resistor Power Dissipation Capacitance (per output) Ouput Impedance VDD = VDDA = VDDO_x = 3.465V VDD = VDDA = VDDO_x = 2.625V Test Conditions Minimum Typical 4 51 9 9 14 Maximum Units pF k pF pF
NOTE: VDDO_X denotes VDDO_A, VDDO_B, VDDO_C.
839893AYI
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REV. A AUGUST 8, 2005
Integrated Circuit Systems, Inc.
ICS839893I
LOW SKEW, 1-TO-13 LVCMOS/LVTTL BUFFER DIVIDER
Outputs FSEL3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fREF Range (MHz) DC - 250 DC - 250 DC - 250 DC - 250 DC - 250 DC - 250 DC - 250 DC - 250 QAx fQAx (MHz) fREF / 1 fREF / 2 fREF / 2 fREF / 4 fREF / 2 fREF / 16 fREF / 8 fREF / 4 QBx fQBx (MHz) fREF / 1 fREF / 2 fREF / 2 fREF / 4 fREF / 2 fREF / 4 fREF / 4 fREF / 8 fREF / 2 fREF / 4 fREF / 16 fREF / 32 fREF / 8 fREF / 16 fREF / 4 fREF / 8 QC fQC0 (MHz) fREF / 8 fREF / 8 fREF / 6 fREF / 8 fREF / 4 fREF / 16 fREF / 8 fREF / 4
TABLE 3. CLOCK FREQUENCY FUNCTION TABLE
Inputs FSEL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSEL1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSEL2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
839893AYI
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REV. A AUGUST 8, 2005
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Integrated Circuit Systems, Inc.
ICS839893I
LOW SKEW, 1-TO-13 LVCMOS/LVTTL BUFFER DIVIDER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO_X + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 3.3V5%, TA = -40C TO 85C
Symbol Parameter VDD Core Supply Voltage VDDO_A, VDDO_B, VDDO_C IDD IDDO_A, IDDO_B, IDDO_C Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3. 3 Maximum 3.465 3.465 155 20 Units V V mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 2.55%, TA = -40C TO 85C
Symbol Parameter VDD VDDO_A, VDDO_B, VDDO_C IDD IDDO_A, IDDO_B, IDDO_C Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 Typical 2. 5 2.5 Maximum 2.625 2.625 150 20 Units V V mA mA
839893AYI
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REV. A AUGUST 8, 2005
Integrated Circuit Systems, Inc.
ICS839893I
LOW SKEW, 1-TO-13 LVCMOS/LVTTL BUFFER DIVIDER
Test Conditions VDD = 3.3V VDD = 3.3V VDD = VIN = 3.465V Minimum Typical 2 -0.3 Maximum VDD + 0.3 0.8 20 0 Units V V A
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 3.3V5%, TA = -40C TO 85C
Symbol Parameter VIH VIL IIH Input High Voltage Input Low Voltage Input High Current CLK0, CLK1, nOE/MR, REF_SEL FSEL0:FSEL3 CLK0, CLK1, Input Low Current nOE/MR, REF_SEL FSEL0:FSEL3 Output High Voltage; NOTE 1
IIL VOH
VDD = 3.465V, VIN = 0V
-5 2.6 0.5
A V V
VOL Output Low Voltage; NOTE 1 Note 1: Outputs terminated with 50 to VDDO_x/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit diagram.
TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 2.5V5%, TA = -40C TO 85C
Symbol Parameter VIH VIL IIH Input High Voltage Input Low Voltage CLK0, CLK1, Input High Current nOE/MR, REF_SEL FSEL0:FSEL3 CLK0, CLK1, Input Low Current nOE/MR, REF_SEL FSEL0:FSEL3 Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 VDD = VIN = 2.625V Test Conditions Minimum Typical 1.7 -0.3 Maximum VDD + 0.3 0.7 20 0 Units V V A
IIL VOH VOL
VDD = 2.625V, VIN = 0V
-5 1.8 0.5
A V V
Note 1: Outputs terminated with 50 to VDDO_x/2. See Parameter Measurement Information, 2.5V Output Load Test Circuit diagram.
839893AYI
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REV. A AUGUST 8, 2005
5
Integrated Circuit Systems, Inc.
ICS839893I
LOW SKEW, 1-TO-13 LVCMOS/LVTTL BUFFER DIVIDER
Test Conditions Minimum DC DC 4.5 Excludes QC 20% to 80% 250 within bank Typical Maximum 250 250 6.5 40 115 465 600 10 10 47 53 Units MHz MHz ns ps ps ps ps ns ns %
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 3.3V5%, TA = -40C TO 85C
Symbol Parameter fOUT fREF tPD tsk(o) tR/tF tPZL, tPZH tPLZ, tPHZ Output Frequency Input Frequency Propagation Delay;NOTE 1 Output Skew; NOTE 2 bank-to-bank any output to QC Output Rise/Fall Time Output Enable Time Output Disable Time
odc Output Duty Cycle All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 output crossing point.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 2.5V5%, TA = -40C TO 85C
Symbol Parameter fOUT fREF tPD tsk(o) tR/tF tPZL, tPZH tPLZ, tPHZ Output Frequency Input Frequency Propagation Delay; NOTE 1 within bank Output Skew; NOTE 2 bank-to-bank any output to QC Output Rise/Fall Time Output Enable Time Output Disable Time 47 20% to 80% 250 Excludes QC Test Conditions Minimum DC DC 5 Typical Maximum 25 0 250 7 40 11 0 410 600 10 10 53 Units MHz MHz ns ps ps ps ps ns ns %
odc Output Duty Cycle All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 output crossing point.
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REV. A AUGUST 8, 2005
Integrated Circuit Systems, Inc.
ICS839893I
LOW SKEW, 1-TO-13 LVCMOS/LVTTL BUFFER DIVIDER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 1.25V5%
VDD, VDDO_A, VDDO_B, VDDO_C
SCOPE
Qx
VDD, VDDO_A, VDDO_B, VDDO_C
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
V
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDDOX 2
DDOX
Qx
2
QX0:QX5
V
DDOX
Qy
2 tsk(o)
QX0:QX5
tsk(b)
VDDOX 2
OUTPUT SKEW
BANK SKEW (where X denotes outputs in the same bank)
Sn (Low-level enabling)
2
2.5V 1.25V 1.25V 0V
V QA0:5, QB0:5, QC
DDOX
t PW
t
PERIOD
tPZH
tPHZ 1.25V
VOL VOH VOH - 0.15V VOL
odc =
t PW t PERIOD
x 100%
Output nDPx (See Note)
NOTE: The output is high except when disabled by the Sn control.
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT ENABLE/DISABLE TIME
CLK0, CLK1
80% 20% tR
80% 20% tF
VDD 2
Clock Outputs
QA0:QA5, QB0:QB5, QC
VDDOX 2 t
PD
OUTPUT RISE/FALL TIME
839893AYI
PROPAGATION DELAY
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Integrated Circuit Systems, Inc.
ICS839893I
LOW SKEW, 1-TO-13 LVCMOS/LVTTL BUFFER DIVIDER APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT INPUTS:
AND
OUTPUT PINS OUTPUTS:
LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached.
CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resister can be tied from the CLK input to ground. CONTROL PINS: All control pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1k resister can be used.
RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
48 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS839893I is: 4615
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REV. A AUGUST 8, 2005
Integrated Circuit Systems, Inc.
ICS839893I
LOW SKEW, 1-TO-13 LVCMOS/LVTTL BUFFER DIVIDER
48 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
839893AYI www.icst.com/products/hiperclocks.html REV. A AUGUST 8, 2005
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Integrated Circuit Systems, Inc.
ICS839893I
LOW SKEW, 1-TO-13 LVCMOS/LVTTL BUFFER DIVIDER
TABLE 8. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature ICS839893AYI ICS839893AYI 48 Lead LQFP tray -40C to 85C ICS839893AYIT ICS839893AYI 48 Lead LQFP 1000 tape & reel -40C to 85C ICS839893AYILF TBD 48 Lead "Lead-Free" LQFP tray -40C to 85C ICS839893AYILFT TBD 48 Lead "Lead-Free" LQFP 1000 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 839893AYI
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REV. A AUGUST 8, 2005

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